Figure 12 shows a logical sequence the steps for designing an ASIC. Steps 1-4 are part of the logical design, steps 5 to 9 are part of the physical design [4].
Figure 12: Steps involved in the design of an ASIC.
- design Entry: A design is loaded into a design system ASIC's can use a hardware description language HDL. Synthesis
- logic: Use an HDL (VHDL or Verilog) and logic synthesis tool produces a list of networks that consists of a description of the logic cells and their interconnections.
- System Partition: Divide a detailed parts of the ASIC. Simulation
- prelayaut: checks if the system is functioning properly.
- Floor Planning: blocks Arrange the list of connection networks on a chip.
- Location: decides the location of the cells in a block.
- Routing: Makes connections between cells and blocks.
- Extraction: determines the resistance and capacitance of interconnects.
- Post-layout simulation: in this step checks whether the design is capable of deaths with the charges added to the interconnections
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