the case of the ASIC but we used to semiconfigurables . These logic cells have been preconfigured and can only alter the settings for all the interconnection masks. By using this method, the designer's work becomes much easier. Even for this kind of ASIC's are two subcategories which are:
- ASIC's based on standard cells.
- ASIC's based on gate arrays.
cell-based ASIC's standard (Standard-Cell-Based ASICs).
Japan is a term colloquially known as CBIC pronounced "sea-bick." Use logic cells composed art such as AND, OR gates, multiplexers and flip-flop's, are known as standard cells [4]. in Figure 2 can be a diagram of a CBIC and the real figure 3 a diagram of a CBIC done with a program for ASIC design.
Figure 2: example internal schema of a CBIC.
Figure 3: View of a CBIC made with a design program.
CBIC areas known as the flexible blocks are composed of columns of standard cells as a brick wall. The areas of standard cells can be used in combination with much larger cells or perhaps known as microcontrollers or microprocessors megaceldas. The megaceldas also called megafunciones, blocks Fully configurable, systems-level macros (SLM's), fixed blocks, cores, or blocks of standard functionality (FSB's).
Designers of these ASIC's only define the place of the standard cells and interconnectivity within a CBIC. However, the standard cell can be located anywhere on the silicon chip, this allows all the masks of a CBIC can be configured for a particular consumer. The CIBIC advantage is that designers save time and reduce the risk when using cell libraries precaracterizadas and proven techniques designed using a cell completely configurable. Additionally, each standard cell can be optimized individually. During the design of each cell in the library, each transistor has been chosen to maximize the speed and the area it occupies in the IC. The disadvantage is the time or cost of design or purchase of standard cell library and the time required to make all layers of the ASIC for the new design.
The standard cell design allows the automation of the assembly process of an ASIC. Groups of these cells can be accommodated in the form of columns, the columns are vertical stacks to form a flexible turn rectangular blocks. Can interface to other standard cell block and another block with other blocks completely configurable. For example, it may be desirable to include a specific interface or microcontroller along with some memory. The microcontroller block can be a fixed megacelda, from memory blocks can be generated using a memory compiler and a custom memory controller that can be built within a standard cell block.
ADB ASIC gate arrays (Gate Array).
In an ASIC gate array-based transistors are predefined in a silicon wafer. Defined patterns of transistors on a gate array and the smallest element is replicated to make the base of the array, and like the drawings of the porcelain on the floor, in this primary design is called the primitive cell. Only the upper layer has defined the interconnections between transistors. To distinguish this type of gate array of other types of gate array that is often called mask gate array or AMS for short in English [4]. The designer chooses a gate array library cells precaracterizadas or art. The logic cells of the gate array library are often called macros. The reason for this is that the design layout of the basal cell is the same for all and the interconnection between them is what can be set freely, the design of an ASIC with gate array is done in a design program is shown in Figure 4.
Figure 4: view the design of a gate array ASICs.
can be spread among several silicon wafers of various consumers as needed. Using prefabricated silicon wafers reduces plating time required to make a MGA. Some of the different types of ASIC's based on existing gate array are:
- grooved gate array.
- unribbed gate array.
- gate array structure.
These terms are given to ASIC according to their mode of construction, for example, when the transistors are arranged in an AMS with a space between the columns of transistors to wire refers to the first term, in the absence of this channel then used the columns of transistors not used for routing connections which corresponds to the second type. In a structured design can be seen both ways of building together within a configurable block.
Figure 5 shows a channeled gate array where only the interconnections can be configured, the interconnect uses predefined spaces between columns cell base and the construction time can take between two days and two weeks.
Figure 5: Schematic of a grooved gate array.
Figure 6 shows the distribution of a gate array without channels, here only some of the interconnection masks can be configured. The logic density is much higher for this type of construction.
Ffigura 6: Outline of a gate array not grooved.
Figure 7 shows a structured gate array, also known as "MasterImage" combines some of the characteristics of the CBIC's and MGA's. One of the disadvantages of the MGA's design is the fixed base cell gate array, this makes the implementation of memory is very difficult and inefficient. In a structured settlement of gates can be used an area dedicated to a specific function which is more convenient for the design of memory cells. In this type of arrangement only interconnections are configurable and configurable blocks can be integrated into the design.
Figure 7: gate array structure.
In the latter type of arrangement can increase the performance of a CBIC but at a lower cost compared to MGA. A disadvantage of an embedded gate array or embedded function is embedded element is fixed, for example, a recessed gate array contains 32 KB of memory, but only needed 16 Kb of memory then wasted half memory. Figure 8 shows a design of a gate array ASICs optimized done in a design program.
Figure 8: Design of a gate array ASICs optimized. The
ASIC's based on gate array and cell-based use predefined cell, but the difference is that in a standard cell can change the size of transistors to optimize performance and speed, but the size of the components in a gate array is fixed. This can result in a tradeoff between the area of \u200b\u200ba gate array on silicon.
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