Here are some of the circuits or elements that are not very well accepted for inclusion in an ASIC.
Frequency Multipliers:
a technique occasionally used is a discrete logical design to produce twice the clock frequency to generate a short pulse using a delay line and an exclusive OR gate. This technique is not required but permitted in ASIC's design when required. Only used in UARTS which requires a special design and test procedure. The frequency multiplication are often implemented using PLL's external. Figure 15 shows an example of the above.
Figure 15: Frequency Multiplier .
Delay Lines:
The exterme delay lines are sensitive to process variations such as temperature. It consists of multiple successive gates produced a latency in the propagation of the signal. This is not necessary when using design techniques sincrinizado. When using delay testing arrangements are more difficult. Figure 16 shows a typical delay line.
Figure 16: delay line.
Monostable:
moestables designs as well as delay lines and frequency multipliers are quite limited in the ASIC design implementation is usually done outside the IC.
Figure 17: Monostable
oscillators on the chip:
Like monostable circuits and delay lines, these are frequency dependent pñrocesos many ASIC manufacturers, providing these oscillators and library patches. It is preferable to use crystal type oscillators.
RS Flip-flop:
The serious disadvantage of using this flip-flop's asynchronously is that its exit status can not be guaranteed when both inputs are a high state. glitches or noise may cause undesirable states at the outputs, so their use in the core is not favorable and is not required because it has the same element but in synchronous version. Figure 18 shows an RS FF.
Figure 18: Flip-flop RS asynchronously.
JK flip-flop:
are undesirable because their use involves more use than the use of a type D in the ASIC, in addition its asynchronous inputs can cause other problems of instability in the system. Figure 19, JK flip-flop.
Figure 19: FF
JK Flip-flop implicit:
Flaw design may occur without the designer take care of the consequences of the creation of a flip-flop implied by connecting a feedback loop in a combinational circuit. The result is an RS flip-flop and should be avoided.
Misuse of control elements:
decoders and comparators are put to work in dangerous situations. This is due to differences in lengths between the data paths and consequent variations in the delays of the gates from their inputs or outputs. Connecting a decoder or a comparator input directly to UCLA a clock or asynchronous deleted, perhaps this can be done to lacher data conditionally on a clock edge, this is a design error with serious consequences. Figure 20 shows one such case.
Figure 20: Misuse elements.
output of a latch clock signal feeding the other:
Conventionally, designers have to try to eliminate dangerous situations and glitches to lacher comparadote exits and decoders using a D-type flip-flop however, the flip-flop output changes during sampling and latch holding time of sampling. The data in the source output of flip-flop is invalid because it sampling started at the point of change and the output of flip-flop is invalid due to violation of the setpoints and sampling. Another problem is when the same data is Lachen in two consecutive clock pulses. The decoder or comparator changes from low to high by the first condition of the sampled data, as there is no change in the output of the decoder then this does not answer the second request. Figure 21 shows the case.
Figure 21: output latch to a clock signal from another.
Gated clock:
When a clock signal controlled by request a latch by a gate creates a bad situation because it appears a short period at the end of two conditional requests due to the delay clock to Q output and the time of D-type flip-flop In figure 22 one can observe a clock controlled by a gate and the condition of another element.
Figure 22: Gated Clock.
negative edge clock:
One way of trying to avoid the problem is using sensitive D latch type trailing edge of the clock. This solves the flip-flop having problems setpoints and sampling of the data but does not solve the problem of sampling on two conditions. The type D
sensitive to trailing edge of the clock has two disadvantages, they reduce by half the clock period available and therefore the circuit as digital filters can not operate at the same speed as a synchronous latch. Negative sides also produce a phenomenon called pulse shaping. This is due to the low mobility of P-type transistors and can produce a differential delay between the response to the rising and descent. in Figure 23 shows the timing diagrams and examples of elements involved.
Figure 23: Problems falling edges.
Clear asynchronous reset using short pulses:
An attempt to erase and conditionally asynchronously against the state of the circuit, is a problem similar to the gated clock. Accordingly there are disadvantages to asynchronous deleted the Flip-flop's RS. Clear
asynchronous-reset pulse length:
In this case the reset function is referred to an additional latch, this is an improvement on the previous version but the disadvantage is that the flip-flop is maintained reset state until it meets next clock period leaving him unavailable for a period. This phenomenon is called dead cycle.
central clock generator:
Many software designs are based on a central generator of clock pulses. The primary generator is an external clock and generates a number of secondary signals fractions of primary clock speed by splitting processes. Although the clock generator I can be designed using synchronous design principles, the central clock generator has a serious disadvantage, the secondary clock signals may be very biased with respect to the primary which means that the primary signal can not be used. Figure 24 shows the case.
Figure 24: central clock generator.
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