December 2007

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1 .- What is an ASIC? History

A Aplication Specific Integrated Circuit or application-specific integrated circuit, better known as ASIC for its acronym in English, is a configurable integrated circuit has been designed for a specific purpose or application specific electronic product.

With recent advances in miniaturization technologies and design tools, the maximum complexity, and hence the functionality in an ASIC has grown from 5,000 logic gates to over 100 million. Modern ASICs often include other elements such as pre:

32-bit processors.
Blocks of RAM, ROM, EEPROM and flash memory .
DSP.
analog amplifiers.
Other types of modules characterized by the consumer such as interfaces or encoders.

This type of ASIC is often called systems on a chip, or SoC for its acronym in English. Digital ASIC designers use hardware description languages \u200b\u200b(HDL) such as Verilog or VHDL, to describe the functionality of these devices [1]. Configuration levels of an ASIC can be in the field of physical (construction of the hardware) or logical level (configuration software) . This depends on the subset or type of ASIC that is used in Figure 1 we can see some views of an ASIC.

Figure 1: Internal view about ASIC's

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2 .- 4 .-

From the 70, has carried out the development of micorelectrónica creating new technologies to achieve developmental, but it was not until 1980 that the Ferranti company engineers began to explore the advantages of the IC design of a configurable and customizable for a particular system or application beyond using standard integrated circuits [2]. Creates microelectronics the pace at which the implementation of IC's standard logic functions can be achieved using one or more IC's configurable. As the VLSI (Very Low Scale Integration) makes it possible to build a system with many smaller components can be combined in many IC's standards within a configurable IC.

company Ferranti Ukraine [3] was the first to produce the first gate arrays. The adaptation of the arrangement is changed occurs when the metal interconnection mask. The ULA (Uncommitted Logic Array) regarded as one of the first IC'ssemiconfigurables developed, initially had a few hundred gates then extend the gamma and make other models that include elements of RAM.

Types and construction of the ASIC's

These IC's are made on a wafer of silicon a few microns thick, each wafer holds a few hundred IC's called dead [4]. Transistors and wiring are made of many layers whose number is between about 10 and 15 all different from one another, arranged one above the other and interconnected as required. Each layer has a pattern that is defined using a mask similar to a photo slide. The first half of the layers defined transistors and the second half of the interconnections between them.

Some of the most prominent types of ASIC's which will be described later are

fully configurable.
Semiconfigurables.
programmable devices.

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3 .- Fully Configurable ASIC

A fully configurable ASIC have probably all configurable logic elements and additionally all layers are configurable. A microprocessor is an example of a fully configurable integrated circuit, it's designers spend many hours to fully configure a section of no more than one square micron.

In this type of ASIC's can design one or all of the logic cells, the circuitry and layout specifically for ASIC [4]. This option allows the designer to ignore the proven ease of use and precaracterizadas cells for all or part of the design. This is profitable only if the logic cells available in the bookstores do not have desirable properties such as speed of calculation or if the cell is very large and consume much energy, may be the case that just any of the designs available cells of the files or libraries to serve the desired purpose. Fewer fully configurable IC's are designed as there are problems with certain special parts of the ASIC that are very difficult to handle.

Historically bipolar technology has been used for precision analog functions. The rationale for this is that all integrated circuits mating features between the different components of IC's is bad, but between the components of the same IC's is excellent. To enhance the difference between them are processed silicon wafer lots where there are several thousands of IC's at the same time with minimal differences in mating with each other.

Mating between transistors is crucial for the operation of a circuit. For the design of IC's should be located transistor pairs side by side. Device physics dictates that a pair of bipolar transistors could always breed more than CMOS transistors of the same size.

bipolar technology is used for the design of ASIC's fully configurable analog because it provides better accuracy. Although the reality is different, despite the bad properties of the use of CMOS technology for analog electronics use has increased two reasons for this are:

technology is more available IC's manufacturing market, many ASIC's are built on this technology.

allows much higher level of integration as required analog and digital functions within a single IC.

For this reason it's ASIC designers have found ways to implement analog functions in CMOS technology using techniques that take advantage of the accuracy of the bipolar analog designs, called BiCMOS technology.

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ASIC ASIC's Semiconfigurables

the case of the ASIC but we used to semiconfigurables . These logic cells have been preconfigured and can only alter the settings for all the interconnection masks. By using this method, the designer's work becomes much easier. Even for this kind of ASIC's are two subcategories which are:

ASIC's based on standard cells.
ASIC's based on gate arrays.

cell-based ASIC's standard (Standard-Cell-Based ASICs).

Japan is a term colloquially known as CBIC pronounced "sea-bick." Use logic cells composed art such as AND, OR gates, multiplexers and flip-flop's, are known as standard cells [4]. in Figure 2 can be a diagram of a CBIC and the real figure 3 a diagram of a CBIC done with a program for ASIC design.

Figure 2: example internal schema of a CBIC.

Figure 3: View of a CBIC made with a design program.

CBIC areas known as the flexible blocks are composed of columns of standard cells as a brick wall. The areas of standard cells can be used in combination with much larger cells or perhaps known as microcontrollers or microprocessors megaceldas. The megaceldas also called megafunciones, blocks Fully configurable, systems-level macros (SLM's), fixed blocks, cores, or blocks of standard functionality (FSB's).

Designers of these ASIC's only define the place of the standard cells and interconnectivity within a CBIC. However, the standard cell can be located anywhere on the silicon chip, this allows all the masks of a CBIC can be configured for a particular consumer. The CIBIC advantage is that designers save time and reduce the risk when using cell libraries precaracterizadas and proven techniques designed using a cell completely configurable. Additionally, each standard cell can be optimized individually. During the design of each cell in the library, each transistor has been chosen to maximize the speed and the area it occupies in the IC. The disadvantage is the time or cost of design or purchase of standard cell library and the time required to make all layers of the ASIC for the new design.

The standard cell design allows the automation of the assembly process of an ASIC. Groups of these cells can be accommodated in the form of columns, the columns are vertical stacks to form a flexible turn rectangular blocks. Can interface to other standard cell block and another block with other blocks completely configurable. For example, it may be desirable to include a specific interface or microcontroller along with some memory. The microcontroller block can be a fixed megacelda, from memory blocks can be generated using a memory compiler and a custom memory controller that can be built within a standard cell block.

ADB ASIC gate arrays (Gate Array).

In an ASIC gate array-based transistors are predefined in a silicon wafer. Defined patterns of transistors on a gate array and the smallest element is replicated to make the base of the array, and like the drawings of the porcelain on the floor, in this primary design is called the primitive cell. Only the upper layer has defined the interconnections between transistors. To distinguish this type of gate array of other types of gate array that is often called mask gate array or AMS for short in English [4]. The designer chooses a gate array library cells precaracterizadas or art. The logic cells of the gate array library are often called macros. The reason for this is that the design layout of the basal cell is the same for all and the interconnection between them is what can be set freely, the design of an ASIC with gate array is done in a design program is shown in Figure 4.

Figure 4: view the design of a gate array ASICs.

can be spread among several silicon wafers of various consumers as needed. Using prefabricated silicon wafers reduces plating time required to make a MGA. Some of the different types of ASIC's based on existing gate array are:

grooved gate array.
unribbed gate array.
gate array structure.

These terms are given to ASIC according to their mode of construction, for example, when the transistors are arranged in an AMS with a space between the columns of transistors to wire refers to the first term, in the absence of this channel then used the columns of transistors not used for routing connections which corresponds to the second type. In a structured design can be seen both ways of building together within a configurable block.

Figure 5 shows a channeled gate array where only the interconnections can be configured, the interconnect uses predefined spaces between columns cell base and the construction time can take between two days and two weeks.

Figure 5: Schematic of a grooved gate array.

Figure 6 shows the distribution of a gate array without channels, here only some of the interconnection masks can be configured. The logic density is much higher for this type of construction.

Ffigura 6: Outline of a gate array not grooved.

Figure 7 shows a structured gate array, also known as "MasterImage" combines some of the characteristics of the CBIC's and MGA's. One of the disadvantages of the MGA's design is the fixed base cell gate array, this makes the implementation of memory is very difficult and inefficient. In a structured settlement of gates can be used an area dedicated to a specific function which is more convenient for the design of memory cells. In this type of arrangement only interconnections are configurable and configurable blocks can be integrated into the design.

Figure 7: gate array structure.

In the latter type of arrangement can increase the performance of a CBIC but at a lower cost compared to MGA. A disadvantage of an embedded gate array or embedded function is embedded element is fixed, for example, a recessed gate array contains 32 KB of memory, but only needed 16 Kb of memory then wasted half memory. Figure 8 shows a design of a gate array ASICs optimized done in a design program.

Figure 8: Design of a gate array ASICs optimized. The

ASIC's based on gate array and cell-based use predefined cell, but the difference is that in a standard cell can change the size of transistors to optimize performance and speed, but the size of the components in a gate array is fixed. This can result in a tradeoff between the area of \u200b\u200ba gate array on silicon.

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5 .- Layer Interconnect Routing and

In ASIC's modern use two, three or more levels of metal interconnect layers, this allows the cables crossing different layers in the same way we use copper in different layers of a printed circuit board. In a CMOS two-level connections to a standard cell inputs and outputs can be made using the second level of interconnect metal. As technology levels the connections can be for the same cell logic. In this way you can make a much more sophisticated routing taking the extra layer of metal layer in Figure 9 shows an example of the distribution of layers of an ASIC in this category.

Figure 9: View the profile of an ASIC

A connection that requires passing through a column of standard cells used a piece of metal that is used to pass a signal through a cell or an empty space in a cell, this is called "feedthrough" location can be seen in Figure 10.

Figure 10: Routing a CBIC Through a cell.

VDD and GND buses within the standard cell normally use the lowest level of interconnection. The width of each column of standard cells can be adjusted to align them using spacers. The power buses are interconnected vertical rails additional energy found in the second layer. Usually the designer can control the number and width of vertical power rails connected to the standard cells for the physical design of the device. A schematic diagram of the energy distribution of a CBIC can be seen in Figure 11.

Figure 11: Distribution clues to a cell.

All masks CBIC can be a configured, they can hold megaceldas such as SRAM, SCSI, MPEG decoders, and be located in the same IC with standard cells. The megaceldas libraries can be supplied by the company that makes the ASIC with full models that are much more advanced and are being tested. The ASIC libraries also provide flexible compilers to generate DRAM SRAM or ROM blocks.

For logic that operates on multiple signals through a data bus using standard cells may not be the style most efficient ASIC design. Some libraries provide ASIC data path compilers that automatically generate data path logic. A library of data path typically contains cells such as adders, subtracter, multiplier and ALU's.

Libraries of standard cells or gate array may contain hundreds of different logic cells, including combinational functions with multiple inputs, and latches and flip-flops with different combinations of reset, preset and clock options. Libraries ASIC companies, provide designers with a date book in electronic format with all functional descriptions along with the timing diagrams for each element contained in their libraries.

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6 .- PLD Programmable Logic Devices

standard IC's are the family of ASIC's that are available in standard configurations from catalogs of parts and are sold in large volumes for many consumers. However, the PLD's can be configured or programmed to create configurable parts for a specific application, the PLD's use different technologies to allow device programming. Among the main features of the PLD's can include:

not have masks or layers or configurable logic cells. Quick
design.
A single large block of programmable interconnections.
They have a matrix of logic macrocells that usually consist of programmable array logic followed by flip-flop or latch.

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7 .- Field Programmable Gate Arrays FPGA

When complegidad programmable gate array increases then called the ASIC and FPGA, and this is the only difference between PLD'sy the FPGA, in fact some companies that manufacture FPGA ASIC's called a complex PLD products [4]. The FPGA is one of the newest members of the family of ASIC's, its importance grew rapidly replacing the use of TTL family in microelectronic systems. Some features of this type of ASIC's are:

None of the masks are configurable by the consumer.
a method is used to program the interconnections and the basic logic cells.
The nucleus is a regular array of basic logic cells that can be implemented as a sequential logic based flip-flop's.
An array of programmable interconnections surrounding the logic cells.
cells surrounding the core programmable device.
design takes only a few hours.

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8 .- Steps for System Design Using a

Figure 12 shows a logical sequence the steps for designing an ASIC. Steps 1-4 are part of the logical design, steps 5 to 9 are part of the physical design [4].

Figure 12: Steps involved in the design of an ASIC.

design Entry: A design is loaded into a design system ASIC's can use a hardware description language HDL. Synthesis
logic: Use an HDL (VHDL or Verilog) and logic synthesis tool produces a list of networks that consists of a description of the logic cells and their interconnections.
System Partition: Divide a detailed parts of the ASIC. Simulation
prelayaut: checks if the system is functioning properly.
Floor Planning: blocks Arrange the list of connection networks on a chip.
Location: decides the location of the cells in a block.
Routing: Makes connections between cells and blocks.
Extraction: determines the resistance and capacitance of interconnects.
Post-layout simulation: in this step checks whether the design is capable of deaths with the charges added to the interconnections

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9 .- Modología ASIC Design ASIC's

An important classification in this context is the methodology used in the process ASIC design [5]. The following three categories to describe it.

static synchronous design: this first category is based on sensitivity of the flanks and database schemas time you single phase. All storage elements are sensitive to the wings of a common clock signal. If the clock stops, the whole system could be in a static state indefinitely, this design technique is also applied to programmable devices which are a very use of ASIC's for many systems. This is an important category because most of the systems designed today are built under this standard.
Static multi Design: these circuits are based on a level detection system multiphase clock. Usually there are two phases of clock but there are cases where it will employ up to four phases. These designs have cascaded latch's which are sensitive to levels of a master clock, these are functionally equivalent to flip-flop's sensitive sides, only a simple modification is required to make the match is sensitive to the flanks . Multiphase levels are really desirable when the developed chip is the heart of the system, such as a microprocessor. The ASIC's are usually used as auxiliary chips in a system.
dynamic multi Design: these dynamic circuits require their clock signals can be extended to maintain their status. This technique is used for propagation of the transistors, storage and pre-bus capacitance. It is the most advanced methodology.

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10 .- Economic Tendensias for the Use of ASIC's

Figure 13 shows a curve that shows the costs associated with the use of each of the main types of ASIC's with respect to quantity.

figure 13: costs of ASIC's with respect to their production number.

Figure 14 reflects the costs of ASIC's about the number of gates contained in a single chip.

Figure 14: Cost of ASIC's in function of the number of gates.

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11 .- Improper technique for ASIC Design with

Here are some of the circuits or elements that are not very well accepted for inclusion in an ASIC.

Frequency Multipliers:

a technique occasionally used is a discrete logical design to produce twice the clock frequency to generate a short pulse using a delay line and an exclusive OR gate. This technique is not required but permitted in ASIC's design when required. Only used in UARTS which requires a special design and test procedure. The frequency multiplication are often implemented using PLL's external. Figure 15 shows an example of the above.

Figure 15: Frequency Multiplier .

Delay Lines:

The exterme delay lines are sensitive to process variations such as temperature. It consists of multiple successive gates produced a latency in the propagation of the signal. This is not necessary when using design techniques sincrinizado. When using delay testing arrangements are more difficult. Figure 16 shows a typical delay line.

Figure 16: delay line.

Monostable:

moestables designs as well as delay lines and frequency multipliers are quite limited in the ASIC design implementation is usually done outside the IC.

Figure 17: Monostable

oscillators on the chip:

Like monostable circuits and delay lines, these are frequency dependent pñrocesos many ASIC manufacturers, providing these oscillators and library patches. It is preferable to use crystal type oscillators.

RS Flip-flop:

The serious disadvantage of using this flip-flop's asynchronously is that its exit status can not be guaranteed when both inputs are a high state. glitches or noise may cause undesirable states at the outputs, so their use in the core is not favorable and is not required because it has the same element but in synchronous version. Figure 18 shows an RS FF.

Figure 18: Flip-flop RS asynchronously.

JK flip-flop:

are undesirable because their use involves more use than the use of a type D in the ASIC, in addition its asynchronous inputs can cause other problems of instability in the system. Figure 19, JK flip-flop.

Figure 19: FF

JK Flip-flop implicit:

Flaw design may occur without the designer take care of the consequences of the creation of a flip-flop implied by connecting a feedback loop in a combinational circuit. The result is an RS flip-flop and should be avoided.

Misuse of control elements:

decoders and comparators are put to work in dangerous situations. This is due to differences in lengths between the data paths and consequent variations in the delays of the gates from their inputs or outputs. Connecting a decoder or a comparator input directly to UCLA a clock or asynchronous deleted, perhaps this can be done to lacher data conditionally on a clock edge, this is a design error with serious consequences. Figure 20 shows one such case.

Figure 20: Misuse elements.

output of a latch clock signal feeding the other:

Conventionally, designers have to try to eliminate dangerous situations and glitches to lacher comparadote exits and decoders using a D-type flip-flop however, the flip-flop output changes during sampling and latch holding time of sampling. The data in the source output of flip-flop is invalid because it sampling started at the point of change and the output of flip-flop is invalid due to violation of the setpoints and sampling. Another problem is when the same data is Lachen in two consecutive clock pulses. The decoder or comparator changes from low to high by the first condition of the sampled data, as there is no change in the output of the decoder then this does not answer the second request. Figure 21 shows the case.

Figure 21: output latch to a clock signal from another.

Gated clock:

When a clock signal controlled by request a latch by a gate creates a bad situation because it appears a short period at the end of two conditional requests due to the delay clock to Q output and the time of D-type flip-flop In figure 22 one can observe a clock controlled by a gate and the condition of another element.

Figure 22: Gated Clock.

negative edge clock:

One way of trying to avoid the problem is using sensitive D latch type trailing edge of the clock. This solves the flip-flop having problems setpoints and sampling of the data but does not solve the problem of sampling on two conditions. The type D

sensitive to trailing edge of the clock has two disadvantages, they reduce by half the clock period available and therefore the circuit as digital filters can not operate at the same speed as a synchronous latch. Negative sides also produce a phenomenon called pulse shaping. This is due to the low mobility of P-type transistors and can produce a differential delay between the response to the rising and descent. in Figure 23 shows the timing diagrams and examples of elements involved.

Figure 23: Problems falling edges.

Clear asynchronous reset using short pulses:

An attempt to erase and conditionally asynchronously against the state of the circuit, is a problem similar to the gated clock. Accordingly there are disadvantages to asynchronous deleted the Flip-flop's RS. Clear

asynchronous-reset pulse length:

In this case the reset function is referred to an additional latch, this is an improvement on the previous version but the disadvantage is that the flip-flop is maintained reset state until it meets next clock period leaving him unavailable for a period. This phenomenon is called dead cycle.

central clock generator:

Many software designs are based on a central generator of clock pulses. The primary generator is an external clock and generates a number of secondary signals fractions of primary clock speed by splitting processes. Although the clock generator I can be designed using synchronous design principles, the central clock generator has a serious disadvantage, the secondary clock signals may be very biased with respect to the primary which means that the primary signal can not be used. Figure 24 shows the case.